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1 ? fn8113.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x4003, x4005 cpu supervisor features ? selectable watchdog timer ?select 200ms, 600ms, 1.4s, off ?low v cc detection and reset assertion ?five standard reset threshold voltages nominal 4.62v, 4.38v, 2.92v, 2.68v, 1.75v ?adjust low v cc reset threshold voltage using special programming sequence ?reset signal valid to v cc = 1v ? low power cmos ?12a typical standby current, watchdog on ?800na typical standby current watchdog off ?3ma active current ? 400khz i 2 c interface ? 1.8v to 5.5v power supply operation ? available packages ?8 ld soic ?8 ld msop ? pb-free plus anneal available (rohs compliant) description these devices combine three popular functions, power-on reset control, wa tchdog timer, and supply voltage supervision. this combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscilla- tor to stabilize before the processor can execute code. the watchdog timer provides an independent protection mechanism for microcontrollers. when the microcontroller fails to restart a timer within a select- able time out interval, the device activates the reset /reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device?s low v cc detection circuitry protects the user?s system from low volt age conditions, resetting the system when v cc falls below the minimum v cc trip point. reset /reset is asserted until v cc returns to proper operating level and stabilizes. five industry stan- dard v trip thresholds are available; however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements, or to fine-tune the thresh- old for applications requiring higher precision. block diagram data register command decode & control logic sda scl v cc reset & watchdog timebase power-on and generation + - reset (x4003) reset low voltage control register watchdog transition detector wp v cc threshold reset logic reset (x4005) v trip watchdog timer reset data sheet may 11, 2006
2 fn8113.1 may 11, 2006 ordering information part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range (v) temp. range (c) package pkg. dwg. # x4003m8-4.5a ach x4005m8-4.5a acq 4.5 to 5.5 4.5 to 4.75 0 to 70 8 ld msop (3.0mm) m8.118 x4003m8z-4.5a (note) dah x4005m8z-4.5a (note) dap 0 to 70 8 ld msop (3.0mm) (pb-free) m8.118 x4003m8i-4.5a aci x4005m8i-4.5a acr -40 to 85 8 ld msop (3.0mm) m8.118 x4003m8iz-4.5a (note) dad x4005m8iz-4.5a (note) dam -40 to 85 8 ld msop (3.0mm) (pb-free) m8.118 x4003s8-4.5a x4003 al x4005s8-4.5a x4005 al 0 to 70 8 ld soic (150 mil) mdp0027 x4003s8z-4.5a (note) x4003 zal x4005s8z-4.5a (note) x4005 zal 0 to 70 8 ld soic (150 mil) (pb-free) mdp0027 x4003s8i-4.5a x4003 am x4005s8i-4.5a x4005 am -40 to 85 8 ld soic (150 mil) mdp0027 x4003s8iz-4.5a (note) x4003 zam x4005s8iz-4.5a (note) x4005 zam -40 to 85 8 ld soic (150 mil) (pb-free) mdp0027 x4003m8 acj x4005m8 acs 4.25 to 4.5 0 to 70 8 ld msop (3.0mm) m8.118 x4003m8z (note) dae x4005m8z (note) der 0 to 70 8 ld msop (3.0mm) (pb-free) m8.118 x4003m8i ack x4005m8i act -40 to 85 8 ld msop (3.0mm) m8.118 x4003m8iz (note) daa x4005m8iz (note) daj -40 to 85 8 ld msop (3.0mm) (pb-free) m8.118 x4003s8 x4003 x4005s8 x4005 0 to 70 8 ld soic (150 mil) mdp0027 x4003s8z (note) x4003 z x4005s8z (note) x4005 z 0 to 70 8 ld soic (150 mil) (pb-free) mdp0027 x4003s8i x4003 i x4005s8i x4005 i -40 to 85 8 ld soic (150 mil) mdp0027 x4003s8iz (note) x4003 zi x4005s8iz (note) x4005 zi -40 to 85 8 ld soic (150 mil) (pb-free) mdp0027 x4003m8-2.7a acl x4005m8-2.7a acu 2.7 to 5.5 2.85 to 3.0 0 to 70 8 ld msop (3.0mm) m8.118 x4003m8z-2.7a (note) dag x4005m8z-2.7a (note) dao 0 to 70 8 ld msop (3.0mm) (pb-free) m8.118 x4003m8i-2.7a acm x4005m8i-2.7a acv -40 to 85 8 ld msop (3.0mm) m8.118 x4003m8iz-2.7a (note) dac x4005m8iz-2.7a (note) dal -40 to 85 8 ld msop (3.0mm) (pb-free) m8.118 x4003s8-2.7a x4003 an x4005s8-2.7a x4005 an 0 to 70 8 ld soic (150 mil) mdp0027 x4003s8z-2.7a (note) x4003 zan x4005s8z-2.7a (note) x4005 zan 0 to 70 8 ld soic (150 mil) (pb-free) mdp0027 x4003s8i-2.7a x4003 ap x4005s8i-2.7a x4005 ap -40 to 85 8 ld soic (150 mil) mdp0027 x4003, x4005
3 fn8113.1 may 11, 2006 x4003s8iz-2.7a (note) x4003 zap x4005s8iz-2.7a (note) x4005 zap 2.7 to 5.5 2.85 to 3.0 -40 to 85 8 ld soic (150 mil) (pb-free) mdp0027 x4003m8-2.7 acn x4005m8-2.7 acw 2.55 to 2.7 0 to 70 8 ld msop (3.0mm) m8.118 x4003m8z-2.7 (note) daf x4005m8z-2.7 (note) dan 0 to 70 8 ld msop (3.0mm) (pb-free) m8.118 x4003m8i-2.7 aco x4005m8i-2.7 acx -40 to 85 8 ld msop (3.0mm) m8.118 x4003m8iz-2.7 (note) dab x4005m8iz-2.7 (note) dak -40 to 85 8 ld msop (3.0mm) (pb-free) m8.118 x4003s8-2.7 x4003 f x4005s8-2.7 x4005 f 0 to 70 8 ld soic (150 mil) mdp0027 x4003s8z-2.7 (note) x4003 zf x4005s8z-2.7 (note) x4005 zf 0 to 70 8 ld soic (150 mil) (pb-free) mdp0027 x4003s8i-2.7 x4003 g x4005s8i-2.7 x4005 g -40 to 85 8 ld soic (150 mil) mdp0027 x4003s8iz-2.7 (note) x4003 zg x4005s8iz-2.7 (note) x4005 zg -40 to 85 8 ld soic (150 mil) (pb-free) mdp0027 note: intersil pb-free plus anneal products em ploy special pb-free material sets; mold ing compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range (v) temp. range (c) package pkg. dwg. # x4003, x4005
4 fn8113.1 may 11, 2006 pin configuration pin description nc v ss v cc sda scl 3 2 4 1 6 7 5 8 nc wp reset 8-pin jedec soic, msop pin (soic/dip) pin tssop pin (msop) name function 1 3 nc no internal connections 2 4 nc no internal connections 3 5 2 reset / reset reset output . reset /reset is an active low/high, open drain output which goes active whenever v cc falls below the min- imum v cc sense level. it will re main active until v cc rises above the minimum v cc sense level for 250ms. reset / reset goes active if the watchdog timer is enabled and sda re- mains either high or low longer than the selectable watchdog time out period. a falling edge of sda, while scl also toggles from high to low followed by a stop condition resets the watchdog timer. reset /reset goes active on power- up and remains active for 250ms after the power supply stabilizes. 463v ss ground 574sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. this pin re- quires a pull up resistor and the input buffer is always active (not gated). watchdog input. a high to low transition on the sda while scl also toggles from high to low follow by a stop condition re- sets the watchdog timer. the absence of this procedure within the watchdog time out period results in reset /reset going active. 685scl serial clock. the serial clock controls the serial bus timing for data input and output. 716wp write protect. wp high prevents changes to the watchdog timer setting. 821v cc supply voltage x4003, x4005
5 fn8113.1 may 11, 2006 principles of operation power-on reset application of power to the x4003/x4005 activates a power-on reset circuit that pulls the reset /reset pin active. this signal provides several benefits. ? it prevents the system micr oprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to stabilization of the oscillator. ? it allows time for an fpga to download its configura- tion prior to initialization of the circuit. when v cc exceeds the device v trip threshold value for 200ms (nominal) the circuit releases reset /reset, allowing the system to begin operation. low voltage monitoring during operation, the x4003/x4005 monitors the v cc level and asserts reset /reset if supply voltage falls below a preset minimum v trip . the reset /reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset /reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit monitors the microproces- sor activity by monitoring the sda and scl pins. the microprocessor must togg le the sda pin high to low periodically, while scl also toggles from high to low (this is a start bit) followed by a stop condition prior to the expiration of the watchdog time out period to prevent a reset /reset signal. the state of two nonvolatile control bits in the control register deter- mine the watchdog timer period. the microprocessor can change these watchdog bits, or they may be ?locked? by tying the wp pin high. figure 1. watchdog restart set v trip level sequence (v cc = desired v trip value) v cc threshold reset procedure the x4003/x4005 is shipped with a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. how- ever, in applications where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x4003/x4005 threshold may be adjusted. the procedure is described below, and uses the application of a nonvolatile control signal. setting the v trip voltage this procedure is used to set the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure will directly make the change. if the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. scl sda .6s .6s start condition stop condition restart 012 4567 scl sda a0h 01234567 01h wp v p = 15-18v 01234567 00h 3 x4003, x4005
6 fn8113.1 may 11, 2006 to set the new v trip voltage, apply the desired v trip threshold voltage to the v cc pin and tie the wp pin to the programming voltage v p . then write data 00hto address 01h. the stop bit following a valid write opera- tion initiates the v trip programing sequence. bring wp low to complete the operation. resetting the v trip voltage this procedure is used to set the v trip to a ?native? voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is some- thing less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the new v trip voltage, apply the desired v trip threshold voltage to the v cc pin and tie the wp pin to the programming voltage v p . then write 00h to address 03h. the stop bit of a valid write operation ini- tiates the v trip programming sequence. bring wp low to complete the operation. figure 2. reset v trip level sequence (v cc > 3v. wp = 15-18v) figure 3. sample v trip reset circuit 01234567 scl sda a0h 01234567 03h wp v p = 15 - 18v 01234567 00h 1 2 3 4 8 7 6 5 x4003/05 v trip adj. v p reset/ 4.7k sda scl c adjust run reset x4003, x4005
7 fn8113.1 may 11, 2006 figure 4. v trip programming sequence control register the control register provides the user a mechanism for changing the watchdog timer settings. watchdog timer bits are nonvolatile and do not change when power is removed. the control register is accessed with a special preamble in the slave byte (1011) and is located at address 1ffh. it can only be modified by performing a control register write operation. only one data byte is allowed for each register write operation. prior to writing to the control reg- ister, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. see "writing to the control register" below. the user must issue a stop after sending the control byte to the register to initiate the nonvolatile cycle that stores wd1 and wd0. the x4003/x4005 will not acknowledge any data bytes written after the first byte is entered. the state of the control register can be read at any time by performing a serial read operation. only one byte is read by each regi ster read operation. the x4003/x4005 resets itself after the first byte is read. the master should supply a stop condition to be con- sistent with the bus protocol, but a stop is not required to end this operation. v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 50mv) execute sequence reset v trip new v cc applied = old v cc applied - error error ?emax -emax < error < emax yes no error emax emax = maximum allowable v trip error 76543 2 10 0wd1wd0 0 0 rwelwel0 x4003, x4005
8 fn8113.1 may 11, 2006 rwel: register write enable latch (volatile) the rwel bit must be set to ?1? prior to a write to the control register. wel: write enable latch (volatile) the wel bit controls the access to the control register during a write operation. this bit is a volatile latch that powers up in the low (dis abled) state. while the wel bit is low, writes the cont rol register will be ignored (no acknowledge will be issu ed after the data byte). the wel bit is set by writing a ?1? to the wel bit and zeroes to the other bits of the control register. once set, wel remains set until eith er it is reset to 0 (by writing a ?0? to the wel bit and zeroes to the other bits of the control register) or until the part powers up again. writes to the wel bi t do not cause a nonvolatile write cycle, so the device is ready for the next opera- tion immediately after the stop condition. wd1, wd0: watchdog timer bits the bits wd1 and wd0 control the period of the watchdog timer. the options are shown below. writing to the control register changing any of the nonvolatile bits of the control regis- ter requires the following steps: ? write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pre- ceeded by a start and ended with a stop.) ? write a 06h to the control register to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cyc le. the zeros in the data byte are required. (operation preceeded by a start and ended with a stop.) ? write a value to the control register that has all the control bits set to the des ired state. this can be rep- resented as 0 xy 0 0010 in binary, where xy are the wd bits. (operation preceeded by a start and ended with a stop.) since this is a nonvolatile write cycle it will take up to 10ms to co mplete. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. if bit 2 is set to ?1? in this third step (0 xy 0 0110) then the rwel bit is set, but the wd1 and wd0 bits remain unchanged. writing a second byte to the control reg- ister is not allowed. doin g so aborts the write opera- tion and returns a nack. ? a read operation occurring between any of the previ- ous operations will not inte rrupt the regi ster write operation. ? the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustrate, a sequ ence of writes to the device con- sisting of [02h, 06h, 02h] will reset all of the nonvola- tile bits in the control regist er to 0. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. serial interface serial interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this fam- ily operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state cha nges during scl high are reserved for indicating start and stop conditions. see figure 5. wd1 wd0 watchdog time out period 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory setting) x4003, x4005
9 fn8113.1 may 11, 2006 figure 5. valid data changes on the sda bus serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device contin uously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 6. serial stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condi tion is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has rel eased the bus. see figure 6. figure 6. valid start and stop conditions serial acknowledge acknowledge is a software convention used to indi- cate successful data transf er. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during t he ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 7. the device will respond with an acknowle dge after recognition of a start condition and the correct con- tents of the slave address byte. acknowledge bits are also provided by the x4003/4005 after correct recep- tion of the control register address byte, after receiving the byte written to the cont rol register and after the second slave address in a read question (see figure 8 and see figure 9.) scl data stable data change data stable sda scl sda start stop x4003, x4005
10 fn8113.1 may 11, 2006 figure 7. acknowledge response from receiver serial write operations slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: ? a device type identifier that is always ?1011?. ? two bits of ?0?. ? one bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte defines the opera- tion to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 8. ? after loading the entire slave address byte from the sda bus, the device compares the input slave byte data to the proper slave byte. upon a correct com- pare, the device outputs an acknowledge on the sda line. write control register to write to the control register, the device requires the slave address byte and a byte address. this gives the master access to register. after receipt of the address byte, the device responds with an acknowledge, and awaits the data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. if wp is high, the control register cannot be changed. a write to the control register will suppress the acknowledge bit and no data in the control register will change. with wp low, a second byte written to the control register terminates the operation and no write occurs. stops and write modes stop conditions that terminate write operations must be sent by the master after sending 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing the write. figure 8. write control register sequence data output from data output from receiver 8 1 9 start acknowledge scl from master 0 slave address byte address data a c k a c k a c k sda bus signals from the slave signals from the master start stop 1 0 0 1 1 0 11 1 1 1 1 1 1 1 x4003, x4005
11 fn8113.1 may 11, 2006 serial read operations the read operation allows the master to access the control register. to conform to the i 2 c standard, prior to issu- ing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write opera- tion. the master issues th e start condition and the slave address byte, receives an acknowledge, then issues the byte address. after acknowledging receipt of the byte address, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowl- edge from the device and then by the eight bit control register. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to figure 9 for the address, acknowledge, and data transfer sequences. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? the wel bit is set to ?0?. in this state it is not possi- ble to write to the device. ? sda pin is the input mode. reset /reset signal is active for t purst . figure 9. control register read sequence data protection the following circuitry has been included to prevent inadvertent writes: ? the wel bit must be set to allow a write operation. ? the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. ? a three step sequence is required before writing into the control register to change watchdog timer or block lock settings. ? the wp pin, when held high, prevents all writes to the control register. ? communication to the device is inhibited below the v trip voltage. ? command to change the control register are termi- nated if in-progress when reset /reset go active. symbol table slave address byte address a c k a c k s t a r t s t o p slave address data a c k s t a r t sda bus signals from the slave signals from the master 0 1 0 0 1 1 0 11 1 1 1 1 1 1 11 1 0 0 1 1 0 1 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x4003, x4005
12 fn8113.1 may 11, 2006 absolute maximum ratings temperature under bias ................... -65c to +135c storage temperature ............ ............ -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10s) .................... 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. d.c. operating characteristics (over the recommended operating condit ions unless otherwise specified.) notes: (1) the device enters the active state after any start, and re mains active until: 9 clock cyc les later if the device selec t bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t wc after a stop that initiates a nonvolatile cycle; or 9 cl ock cycles after any start that is not followed by the correct dev ice select bits in the slave addres s byte. (3) v il min. and v ih max. are for reference only and are not tested. symbol parameter v cc = 1.8 to 3.6v v cc = 2.7 to 5.5v unit test conditions min max min max i cc (1) active supply current read control register 0.5 1.0 ma f scl = 400khz nonvolatile, sda = open i cc2 (1) active supply current write control register 1.5 3.0 ma i cc3 (2) operating current ac (wdt off) 11a i cc4 (2) operating current dc (wdt off) 11av sda = v scl = v cc others = gnd or v sb i cc5 (2) operating current dc (wdt on) 10 20 a i li input leakage current 10 10 a v in = gnd to v cc i lo output leakage current 10 10 a v sda = gnd to v cc device is in standby (2) v il (3) input low voltage -0.5 v cc x 0.3 -0.5 v cc x 0.3 v v ih (3) input high voltage v cc x 0.7 v cc + 0.5 v cc x 0.7 v cc + 0.5 v v hys schmitt trigger input hysteresis fixed input level v cc related level 0.2 .05 x v cc 0.2 .05 x v cc v v ol output low voltage 0.4 0.4 v i ol = 3.0ma (2.7-5.5v) i ol = 1.8ma (1.8-3.6v) recommended operating conditions temperature min. max. commercial 0c 70c industrial -40c +85c option supply voltage limits -1.8 1.8v to 3.6v -2.7 and -2.7a 2.7v to 5.5v blank and -4.5a 4.5v to 5.5v x4003, x4005
13 fn8113.1 may 11, 2006 capacitance (t a = 25c, f = 1.0 mhz, v cc = 5v) note: (4) this parameter is periodically sampled and not 100% tested. equivalent a.c. load circuit a.c. test conditions a.c. characteristics (continued) (over recommended operating conditions, unless otherwise specified) notes: (5) typical values are for t a = 25c and v cc = 5.0v (6) cb = total capacitance of one bus line in pf. symbol parameter max. unit test conditions c out (4) output capacitance (sda, reset /reset) 8 pf v out = 0v c in (4) input capacitance (scl, wp) 6 pf v in = 0v 5v 4.6k ? reset 100pf sda 1533 ? 100pf 5v for v ol = 0.4v and i ol = 3 ma reset input pulse levels 0.1v cc to 0.9v cc input rise and fall times 10ns input and output timing levels 0.5v cc output load standard output load symbol parameter 100khz 400khz unit min. max. min. max. f scl scl clock frequency 0 100 0 400 khz t in pulse width suppression time at inputs n/a n/a 50 ns t aa scl low to sda data out valid 0.1 0.9 0.1 0.9 s t buf time the bus free before start of new transmission 4.7 1.3 s t low clock low time 4.7 1.3 s t high clock high time 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:dat data in setup time 250 100 ns t hd:dat data in hold time 5.0 0 s t su:sto stop condition setup time 0.6 0.6 s t dh data output hold time 50 50 ns t r sda and scl rise time 1000 20 +.1cb (6) 300 ns t f sda and scl fall time 300 20 +.1cb (6) 300 ns t su:wp wp setup time 0.4 0.6 s t hd:wp wp hold time 0 0 s cb capacitive load for each bus line 400 400 pf x4003, x4005
14 fn8113.1 may 11, 2006 timing diagrams bus timing wp pin timing write cycle timing nonvolatile write cycle timing note: (7) t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless ac knowledge polling is used. symbol parameter min. typ. (1) max. unit t wc (7) write cycle time 5 10 ms t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t a t r t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start scl sda t wc 8 th bit of last byte ack stop condition start condition x4003, x4005
15 fn8113.1 may 11, 2006 power-up and po wer-down timing reset /reset output timing note: (8) this parameter is periodically sampled and not 100% tested. sda vs. reset/reset timing symbol parameter min. typ. max. unit v trip reset trip point voltage, x4003-4.5a, x4005-4.5a reset trip point voltage, x4003, x4005 reset trip point voltage, x4003-2.7a, x4005-2.7a reset trip point voltage, x4003-2.7, x4005-2.7 reset trip point voltage, x4003-1.8, x4005-1.8 4.5 4.25 2.85 2.55 1.7 4.62 4.38 2.92 2.62 1.75 4.75 4.5 3.0 2.7 1.8 v v v t purst power-up reset time out 100 200 400 ms t rpd (8) v cc detect to reset/output 500 ns t f (8) v cc fall time 10 ms t r (8) v cc rise time 0.1 ns v rvalid reset valid v cc 1v v cc t purst t purst t r t f t rpd reset 0 volts v trip v rvalid v rvalid reset sda t cst reset t wdo t rst t wdo t rst scl reset x4003, x4005
16 fn8113.1 may 11, 2006 reset/reset output timing v trip programming timing diagram v trip programming parameters symbol parameter min. typ. max. unit t wdo watchdog time out period, wd1 = 1, wd0 = 1 (factory setting) wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 100 450 1 off 200 600 1.4 300 800 2 ms ms sec t cst cs pulse width to reset the watchdog 400 ns t rst reset time out 100 200 400 ms parameter description min. max. unit t vps v trip program enable voltage setup time 1 s t vph v trip program enable voltage hold time 1 s t tsu v trip setup time 1 s t thd v trip hold (stable) time 10 ms t wc v trip write cycle time 10 ms t vpo v trip program enable voltage off time (between successive adjustments) 0 s t rp v trip program recovery period (between successive adjustments) 10 ms v p programming voltage 15 18 v v tran v trip programmed voltage range 1.7 5.0 v v ta1 initial v trip program voltage accuracy (v cc applied - v trip ) (programmed at 25c.) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [(v cc applied - v ta1 ) - v trip . programmed at 25c.) -25 +25 mv v tr v trip program voltage repeatability (successive program operations. programmed at 25c.) -25 +25 mv v tv v trip program variation after programming (0 -75c). (programmed at 25c) -25 +25 mv v trip programming parameters are periodically sampled and are not 100% tested. v cc (v trip ) wp t tsu t thd t vph t vps v p v trip t vpo scl sda a0h 01h or 03h 00h t rp x4003, x4005
17 fn8113.1 may 11, 2006 x4003, x4005 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 2 01/03
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8113.1 may 11, 2006 x4003, x4005 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994

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